Processing technology for semiconductor integrated circuits has been steadily shrinking such that the area that a transistor occupies is very small. In a typical integrated circuit design, one of the most important design criteria is speed. The number of gates and transistors is of less importance than minimizing the delay through a functional block. That is, speed or delay minimization is now more important than area considerations in an integrated circuit. Functional blocks in semiconductor integrated circuits are often designed to minimize the timing delay of the resultant output. As a result, area-saving designs are now often overlooked.
In some cases, a particular data path block may not fall into the critical timing path. That is, slower logic designs may be used for a functional block and the overall timing requirements for the data path can still be met.
It is desirable to consider the signal timing along data paths during the logical synthesis of functional blocks in integrated circuits.